This invention relates to command signal generators for memory devices, and more particularly, to a command signal generator that generates a sequence of memory device commands that may vary as a function of clock speed.
In the operation of a dynamic random access memories (xe2x80x9cDRAMsxe2x80x9d), specific functions must occur in a predetermined sequence. These functions are generally performed responsive to respective command signals issued by a command generator. The timing of the command signals is generally controlled by a clock signal either registered to an edge of the clock signal or occurring a predetermined time after an edge of the clock signal. The rate at which the DRAM may process commands is limited by the amount of time it takes to perform functions responsive to the commands. For most functions, the minimum times to perform the functions are specified by the manufacturer of the DRAM. However, since the commands are generally issued responsive to clock signals, the amount of time that the DRAM has to perform its functions is controlled by the clock speed. For example, as illustrated in FIG. 1A, a memory read command 10 is issued by a conventional memory controller and is registered with a clock signal 12 at time t0. As further shown in FIG. 1A, it requires four clock cycles to complete the read operation because of the many operations that must occur in a DRAM before data can be read from the DRAM. Thus, a data bit 14 is not present on the data bus until time t1. The elapsed time from issuing the read command 10 to the complete processing of the command by applying the data bit 14 to the data bus is therefore xcex94ta. The elapsed time could be reduced by increasing the speed of the clock 12. However, regardless of the speed of the clock, the DRAM requires a certain minimum time to complete its functions. Speeding the clock up beyond that point will not reduce the amount of time required to perform those functions.
Although DRAMs are operating at optimum speed when the clock is at or near its maximum speed, they operate a far from optimum speed responsive to slower clock speeds. With reference to FIG. 1B, a clock signal 20 has a speed or frequency only half that of the clock 12 in FIG. 1A. Once again, a read command 22 is registered with the clock 20 at time t0, and a data bit 24 is applied to the data bus four clock cycles later. However, because of the slower speed clock 20, the data bit 24 is not applied to the data bus until t2. As a result of the slower clock speed, the elapsed time between issuing of the read command 22 and complete processing of the command is xcex94tb which is twice the duration of xcex94ta. Thus, by employing a fixed relationship between a clock signal and the issuing of command signals, conventional DRAMs often operate at far from optimum speed when they receive a relatively slow clock signal.
It will be understood by one skilled in the art that the timing diagrams of FIGS. 1A and 1B omit a large number of other signals applied to the DRAM. These signals have been omitted for purposes of brevity. Also, one skilled in the art will understand that the command signals 10, 22 are, in reality, composed of a combination of other signals which are commonly referred to as simply a command. The exact nature of these signals will depend on the nature of the DRAM, but the principle explained above is applicable to all type of DRAMs, including asynchronous DRAMs, synchronous DRAMs, and packetized DRAMs. Also, although the problem resulting from issuing command signals according to a fixed relationship with the clock signal has been explained with reference to DRAMs, the explanation of the problem as well as the solution provided by the preferred embodiment of the invention are applicable to other integrated circuits that issue command signals or the like responsive to a clock signal.
A command generator for generating command signals for a memory device includes a sequencer generating a sequence of command signals responsive to a clock signal that may have one of a plurality of clock speeds. Each of the sequences of command signals preferably corresponds to a respective clock speed, and the sequencer selects one of the sequences as a function of the clock speed. The sequencer may include a counter and a decoder. The counter receives the clock signal and provides a counter value that increments or decrements responsive to the clock signal. The decoder generates one of a plurality of sequences of command signals, with the command signals in each sequence corresponding to respective counter values. Each of the sequences of command signals corresponds to a respective clock speed, and the decoder selects one of the sequences as a function of the clock speed. Thus, the correspondency between each command signal and its respective counter value is a function of the clock speed. The command generator may also include a counter load circuit coupled to the counter. The counter load circuit loads an initial count into the counter that is a function of the clock speed. The counter then increments or decrements from the initial value responsive to the clock signal. The command generator may also include a counter enable circuit generating a counter enable signal to permit the counter to increment or decrement responsive to the clock signal. The counter enable circuit MAY include a latch circuit and a counter start circuit. The latch circuit generates the counter enable signal responsive to a start signal and terminates the counter enable signal responsive to a stop signal. The counter start circuit generates the start signal and includes a clock detector detecting predetermined portions of the clock signal, and a variable delay enable circuit coupled to the clock detector. The variable delay enable circuit generates the start signal responsive to one of the detected predetermined portions of the clock signal after a predetermined number of cycles of the clock signal have elapsed from receiving a flag signal. The command generator may be used in any type of dynamic random access memory or other circuit which may be part of a computer system.